"hardware description languages" Papers

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QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation

Yaoyu Zhu, Di Huang, Hanqi Lyu et al.

NeurIPS 2025posterarXiv:2505.24183
14
citations

VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification

Patrick Yubeaton, Andre Nakkab, Weihua Xiao et al.

NeurIPS 2025posterarXiv:2505.20302
5
citations